1. Field of the Invention
The present invention relates to a flash memory device, and more particularly, to a flash memory device having a row decoder shared by at least two blocks.
2. Description of the Related Art
Flash memory devices program and erase data using the tunneling phenomenon. Based on advantages of flash memory devices, such as superior data preservation, low power consumption, and strong durability against external shock, flash memory devices are typically suitable as auxiliary memory devices of portable devices. The size of a memory cell of a NAND flash memory device, in which a predetermined number of memory cells are connected in series, is relatively small as compared to that of a NOR flash memory device, in which the memory cells are connected in parallel. Thus, the NAND flash memory device exhibits high integrity, and is generally more useful as a large capacity auxiliary memory device.
In a NAND flash memory device, multiple memory cells serially connected to a single bit line constitute a single string, multiple memory cells connected to a single word line constitute a page. A memory cell array is divided into blocks, each block being formed by multiple pages. In the NAND flash memory configured as described above, a reading operation and a programming operation are performed by the page and an erase operation is performed by the block.
For the large capacity of the NAND flash memory device, mats are arranged. Each mat includes multiple blocks, which share bit lines. For example, referring to FIG. 1, in the layout of NAND flash memory device 100, at least two mats, first mat 10 and second mat 20, are arranged. A first row decoder 12 and a first pass transistor unit 14, and a second row decoder 22 and a second pass transistor unit 24, are respectively arranged close to the first mat 10 and the second mat 20.
Each of the first and second row decoders 12 and 22 selects one of the word lines according to address information, and provides word line voltages to selected and unselected word lines according to the operation mode. For instance, in a program operation mode, each of the first and second row decoders 12 and 22 provides a program voltage Vpgm of about 18 V, for example, to a selected word line and a pass voltage Vpass of about 10 V, for example, to an unselected word line. In a read operation mode, each of the first and second row decoders 12 and 22 provides a ground voltage VSS to a selected word line and a read voltage Vread of about 4.5 V, for example, to the unselected word line. The program voltage Vpgm, the pass voltage Vpass and the read voltage Vread are higher than a power voltage VDD of about 3 V, for example.
To provide a voltage higher than the power voltage VDD to the word lines, the first and second row decoders 12 and 22 include a block word line boosting circuit capable of switching a high voltage. The block word line boosting circuit generates a high voltage block word line signal. Each of the first and second pass transistor units 14 and 24 is turned on in response to a block word line signal provided by the first and second row decoders 12 and 22, and applies the program voltage Vpgm, the pass voltage Vpass, and the read voltage Vread provided by the first and second row decoders 12 and 22 to the selected word line and the unselected word lines of the first and second mats 10 and 20.
As the semiconductor manufacturing process develops, the design rule for the memory cell array in each of the first and second mats 10 and 20 decreases. Accordingly, the layout area of each of the first and second mats 10 and 20 decreases. However, since the layout area of the block word line boosting circuit of each of the first and second row decoders 12 and 22 is relatively large, the layout area of each of the first and second row decoders 12 and 22 is not decreased at the rate at which the layout area of each of the first and second mats 10 and 20 decreases. As a result, the first and second row decoders 12 and 22 restrict reduction of the layout area of the NAND flash memory device 100.